The present invention relates to digitally decoding of data information from serial digital bitstreams, and more particularly to low jitter data extraction from serial digital bitstreams.
Prior methods for digitally decoding clock or data information from a serial digital bitstream using asynchronous digital techniques have had the undesirable effect of adding jitter to the resulting output. Information may be encoded into serial bitstreams in a variety of ways. The more efficient methods are often more complex in their structure. For example, the individual bit cells may be of varying width or the polarity of the signal may be unknown. For these and other reasons it frequently is advantageous to use digital techniques to recover information from a serial bitstream. One technique, known as digital sampling, uses a higher frequency clock to "sample" the lower speed serial bitstream. The computational efficiency of this method has been used successfully to decode AES/EBU audio and has been previously disclosed in U.S. Pat. No. 5,465,268 issued Nov. 7, 1995 to Joe L. Rainbolt entitled "Digital Decoding of Biphase-Mark Encoded Serial Digital Signals." A disadvantage in some applications of the sampling method is that the resolution of the samples is limited by the sample clock itself. This leads to a temporal uncertainty (jitter) of at least one clock sample period in the decoded output. This jitter is caused by the precession of the sample phase relative to the phase of the bitstream data which results from the sample clock and bitstream data being asynchronous. It is possible to remove this jitter using a buffer memory. However that requires additional circuitry.
What is desired is a digital decoding method for extracting clock and data information from serial bitstreams that uses a digital sampling technique that does not introduce sampling clock jitter.